The conservation of power in microprocessor-based systems sourced by batteries or other limited power supplies has been a continuous, iterative, and progressive science. As system functionality has improved, users have integrated those systems into their lives, resulting in increased power demand. Balancing increased functionality against this increased power demand requires a combination of innovative hardware design and software methods to both deliver the capabilities the user requires while minimizing the energy used to deliver it. Although systems have changed through the years, from luggable PCs to notebooks and a variety of hand held information appliances, the opposing forces of increasing user expectations and system power demands have not.
A variety of systems ranging from embedded controllers to screen phones and data enabled phones to the latest incarnation of the "PDA," the Hand Held PC, have significant power efficiency requirements, particularly in the last category of device.
User demand for system capabilities has driven power consumption in the past and will drive power consumption on these systems in the future. Higher contrast (or backlit, or color) displays, high speed infrared transceivers, more advanced audio functions with on-board amplification, bigger cache memory sub-systems, I/O coprocessor and higher speed processors are examples of components that increase power consumption in systems. In addition, higher speed net connections quickly dissipate the energy of a battery.
In the prior art, the power management of devices attached to an electronic system, such as a computer, has typically been accomplished in a way that is processor and operating system dependent, and generally with the use of dedicated silicon in the system. Such prior art power management systems use costly hardware timers, and a mechanism called SMI (system management interrupt) mode which is unique to the X86 processor architecture. A combination of hardware timers is used, with one timer disposed on each device to be power managed. Each of the timers is set to generate either an SMI or an IRQ to notify a device driver associated with that device or firmware code, when some power management event has occurred for that device.
A power management framework has been designed into Windows CE.TM. operating system. The Windows CE operating system defines a variety of APIs for applications and drivers to call to invoke power management events. Because Windows CE is designed to be run on a variety of CPU architectures, there is no reliance on traditional X86 power management triggers, such as SMI (system management interrupt) or an Advanced Power Management compliant method of communicating power managed events.
With this cross platform architecture, Windows CE has focused power management on simplified system power state definitions and relies on individual device drivers and application OPEN/CLOSE actions to control power to system devices. For example, when an audio I/O device is called, the OPEN/CLOSE actions of the application can turn the audio device ON/OFF. In the case of the running of multiple applications, however, there are scenarios where devices will remain OPEN or ON even though they are not in use. In this situation the power efficiency of the system drops.
User interaction to control power in Windows CE is via a Control Panel (or status bar icon) applet that enables the user to set the overall SUSPEND/OFF time-out of the system and view the basic battery status.
However, a problem for developers of Windows CE systems is that all of the code below the Windows CE defined API must be developed for each device, for each CPU, and for each OEM platform by either an OEM or by a third party.
Accordingly, the prior art power management systems are either processor specific or operating system specific. The deployment of such systems is costly and complex and places an undue burden on chipset vendors.